Speaker: Long Kong
Affiliation: Ph.D. Candidate - UCLA
Abstract: Recent developments in RF receiver design have eliminated all on-chip inductors except for that used in the local oscillator. This research addresses the “last inductor” problem and proposes both integer-N and fractional-N synthesizer architectures that achieve a phase noise and figure of merit (FOM) comparable to those of LC-VCO-based realizations.
The use of ring oscillators instead of LC implementations offers numerous advantages: smaller area, much less coupling to and from other circuits, a much wider tuning range, straightforward generation of multiple phases, and the ability to multiplex several small rings so as to cover multiple bands with minimal area penalty. However, the far inferior FOM of rings has discouraged their use in RF synthesis. The loop bandwidth of traditional type-II PLLs is bounded by “Gardner’s limit” to fREF/10, and typically less than fREF/20 to suppress the reference spurs, thus failing to reduce the ring’s phase noise sufficiently.
A new wideband integer-N synthesizer is introduced to sufficiently suppress the ring’s phase noise. It employs an exclusive-OR (XOR) phase detector and a master-slave sampling filter (MSSF) to achieve a lock range of 2-3 GHz, a loop bandwidth equal to one half of the reference frequency, and a locked phase noise of -114 dBc/Hz up to 10-MHz offset with a 3-stage ring oscillator. Realized in 45-nm CMOS technology, the design uses a harmonic trap to suppress reference sidebands to less than -65 dBc while consuming 4 mW.
The wideband architecture has been successfully extended to a fractional-N loop as well. A ring-oscillator-based cascaded synthesizer incorporates a digital synchronous delay line and an analog noise trap to suppress the quantization noise of the SD modulator. Realized in 45-nm CMOS technology, the synthesizer exhibits an in-band phase noise of -109 dBc/Hz and an integrated jitter of 1.68 psrms at 2.4 GHz with a power consumption of 6.4 mW.
Biography: Long Kong received his B.E. degree in Microelectronics from Shanghai Jiao Tong University, Shanghai, China in 2011, and his M.S. degree in Electrical Engineering from University of California, Los Angeles in 2013. He is currently a Ph.D. candidate in the Department of Electrical Engineering under Professor Behzad Razavi. His research interests include frequency synthesis for wireless/wireline systems and data converters.
Date(s) - Feb 24, 2016
9:00 am - 11:00 am
E-IV Maxwell Room #57-124
420 Westwood Plaza - 5th Flr. , Los Angeles CA 90095