Speaker: Weicong Li
Affiliation: Ph.D. Candidate

Abstract: Over the last 50 years, conventional scaling (Moore’s law) has provided continuous improvement in semiconductor device/circuit technology and has resulted in unprecedented advancement in electronic systems.  However, as transistors scale below 45nm, the non-scalability of subthreshold swing (SS) in conventional MOSFETs has resulted in increased power consumption. Power/thermal issue has become one of the major roadblocks for the scaling of the devices. Therefore, novel devices with steep SS are highly desirable as they offer the same current drive with a reduced supply voltage (VDD) while maintaining a reasonable IOFF. Among all potential device solutions, including negative capacitance FETs (NC-FETs) and NEMS. Tunnel FETs (TFET) have been widely regarded as the most promising candidates, especially for the power-sensitive Internet of things (IoTs) applications.

State-of-the-art TFETs, both group IV and group III-V-based, have been examined to identify the limitations of the previously proposed devices. SiGe-based device solution is identified as the most promising solution because of its FinFET/GAA compatibility, mature synthesis techniques, and tunable bandgap. Compared with III-V-based TFETs, it is more likely to be adopted by future VLSI technologies. TFET with a counter-doped SiGe-pocket is proposed to take the full advantage of the SiGe material system. By adopting the counter-doped SiGe pocket, both tunneling barrier height and width are reduced, which results in significant improvement in ION as well as SS. Vertical p-type TFET with a counter-doped Si0.8Ge0.2 pocket has been experimentally demonstrated. The vertical doping/composition profile was achieved by in-situ doped RPCVD. Improvement in transfer characteristics has been observed when compared with Si TFET and TFET with an intrinsic Si0.8Ge0.2 pocket. It provides a potential device solution for low power logic applications.

Biography: Weicong Li received the B.S. and M.S. degrees in electrical engineering from the University of California Los Angeles, California, USA, in 2012 and 2014, respectively, where he is currently pursuing the Ph.D. degree in electrical engineering. His current research interests include deeply scaled novel CMOS design for high-performance and steep-slope devices for low-power logic applications.

For more information, contact Prof. Jason Woo ()

Date/Time:
Date(s) - Dec 02, 2019
2:00 pm - 4:00 pm

Location:
E-IV Tesla Room #53-125
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095