Siva Chandra Jangam (Advisor: Prof. Subramanian Iyer, UCLA Center for Integration and Performance Scaling (CHIPS)) won the ECTC Best Student Paper Award for the paper titled “Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme” at the 2018 IEEE 68th Electronic Components and Technology Conference held in San Diego, CA.
This latest work describes the performance and power benefits of the Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF) proposed by a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. Dramatic improvements in bandwidth, latency, and power are achievable through this integration scheme where small dielets (1-25 mm2) are attached to a rigid Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 μm) and short inter-die distance (50-500 μm) using solderless metal-to-metal thermal compression bonding (TCB).
Simulations showed that links in the Si-IF with short wire-lengths (5-25x) improvement in data bandwidth. This can improve system performance (>20x) when compared to PCB-style integration and may even approach single die SoC metrics in some cases. Furthermore the protocol is simple and non-proprietary. The research realizes that this scheme enables heterogeneous system integration using a dielet based assembly method and provides significant reduction in design and validation cost.System-level analysis of heterogeneous integration scheme promises power benefits of more than 15% even for very small systems.