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Abidi, Asad

Asad Abidi.jpg

Asad Abidi, Distinguished Chancellor's Professor

Third World Academy of Science, 2009
National Academy of Engineering, 2007
IEEE Donald O. Pederson Award in Solid State, 2007
Fellow, IEEE, 1996

Office: 53-141 Engr. IV, Phone: 310.825.9490, Email



Asad A. Abidi received the B.Sc. (with Honors) degree from Imperial College, London, U.K. in 1976, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1978 and 1981, respectively.

He was at Bell Laboratories, Murray Hill, NJ, from 1981 to 1984 as a Member of Technical Staff in the Advanced LSI Development Laboratory. Since 1985, he has been with the Electrical Engineering Department of the University of California, Los Angeles, where he is Professor. He was a Visiting Faculty Researcher at Hewlett Packard Laboratories in 1989. His research interests are in CMOS RF design, data high-speed analog integrated circuit design, conversion, and other techniques of analog signal processing.

Dr. Abidi was the Program Secretary for the International Solid-State Circuits Conference from 1984 to 1990, and General Chairman of the Symposium on VLSI Circuits in 1992. He was Secretary of the IEEE Solid-state Circuits Council from 1990 to 1991. From 1992 to 1995, he was Editor of the IEEE Journal of Solid-state Circuits.

Research Interests

Professor Abidi's research interests are focused on the technology of RF-CMOS integrated circuits, including development of a single chip 900 MHz transceiver for frequency-hopped, spread spectrum communications at data rates of up to 160 kb/s. The mixed analog/digital transceiver, implemented in a standard CMOS process, encompasses all the functions between antenna and the baseband signal processing. Current research focuses on CMOS ICs for very high bit rate integrated transceivers at 2.4 GHz, supporting data rates in excess of 10 Mb/s, using adaptive techniques and complex modulation methods. An important recent accomplishment in disk drive signal processing is the demonstration of a low power 160 Mb/s front end for EPR-4 partial response signaling. The CMOS IC contains a new equalizer whose coefficients may be programmed or adapted, and a discrete time clock recovery circuit. In data conversion research, the first CMOS 10 bit, 100 MHz A/D converter with near Nyquist performance has been demonstrated. Working architectures and circuits are being extended to low power and compact implementations of second generation A/D converters with a similar performance.

Awards and Recognitions

  • 2009 Third World Academy of Sciences
  • 2008 UCLA HSSEAS Lockheed Martin Award for Excellence in Teaching
  • 2007 National Academy of Engineering
  • 2007 IEEE Donald O. Pederson Award
  • 2002 ISSCC Top Ten Author
  • 2000 IEEE Third Millennium Medal
  • 1998 Design Contest Award at the the Design Automation Conference
  • 1997 ISSCC Jack Raper Outstanding Technology Directions Paper Award
  • 1997 IEEE Donald G. Fink Prize Award
  • 1996 Best Paper Award of the 21st European Solid State Circuits Conference
  • 1996 IEEE Fellow
  • 1988 TRW Award for Innovative Teaching


  • A. A. Abidi, P. R. Gray, R. G. Meyer, editors, Integrated Circuits for Wireless Communications, IEEE Press, NY, 1998.
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