New Low-Power Techniques for High-Speed Wireline Receivers

Speaker: Atharav
Affiliation: Ph.D. Candidate

Abstract:  With the rapidly increasing Internet traffic and storage volume, the aggregate I/O bandwidth requirements in wireline systems have been climbing at a rate of approximately 2-3 times every two years.  Thus, the power consumption of wireline transceivers has become increasingly more critical as higher data rates and a larger number of lanes per chip are sought. This issue is further intensified by the trade-offs between the channel loss and the power dissipation, especially in the receive path. While PAM4 signaling is attractive for lossier channels, it has mostly dictated receiver designs incorporating analog-to-digital converters (ADCs) with high power numbers. Non-return-to-zero (NRZ) receiver, on the other hand, can be realized in the analog domain, potentially consuming less power, but they must deal with a greater channel loss.

This research introduces a 56-Gb/s NRZ receiver that draws 50 mW while exhibiting bit error rate (BER) of less than 10^-12 for a channel loss of 25 dB at 28 GHz and 13.5 dB at 14 GHz. Such a receiver can compete with PAM4 counterparts and/or serve as part of 112-Gb/s systems that must also support 56-Gb/s NRZ reception. This work demonstrates a threefold improvement in the power efficiency.

Biography:  Atharav received his B.E. degree in Electronics and Communications Engineering from BITS-Pilani, Hyderabad, India in 2012. He then joined Texas Instruments (TI), Bangalore as an intern to develop high precision comparators. He also worked at Redpine Signals, Hyderabad, India as a design engineer where he focused designing high speed, low power SAR ADCs. In summer 2014, he interned at Silicon Labs, Sunnyvale, US where he worked on switched-cap Bandgap References. He completed his Master in Electrical Engineering at UCLA in 2015 and joined CCL lab as a PhD student. In summer 2015, he interned at Broadcom, Irvine, US in wideband-ADC team. Atharav is also a recipient of Analog Devices outstanding student designer award in February 2017. His current research interest is high-speed wireline equalizers and CDRs.

For more information, contact Prof. Behzad Razavi (razavi@ee.ucla.edu)

Date/Time:
Date(s) - Mar 06, 2020
12:00 pm - 2:00 pm

Location:
E-IV Maxwell Room #57-124
420 Westwood Plaza - 5th Flr. , Los Angeles CA 90095