A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC

Speaker: Prof. Gabor C. Temes
Affiliation: School of EECS, Oregon State University

Abstract:  An active noise-shaping successive-approximation-register (SAR) analog-to-digital converter is described. Instead of binary-weighted capacitors, it uses two equal-valued capacitors as the embedded digital-to-analog converter (DAC). Thus, the capacitance spread in the DAC is much smaller than that of the conventional binary-weighted capacitor array, and the mismatch error can be greatly reduced. The circuit provides first-order noise shaping, which can improve the ADC’s linearity even for a small oversampling ratio. Also, the   proposed architecture uses a monotonic approximation procedure, which requires fewer conversion steps than for a conventional SAR ADCs. The ADC was fabricated in 0.18 um CMOS technology. For a 2 kHz signal bandwidth, it achieved a 78.8 dB SNDR. It consumes 74.2 mW power from a 1.5 V power supply. The performance can be drastically improved by introducing digital calibration and higher-order noise shaping. These topics will also be discussed.

Biography:  Gabor C. Temes received the Ph.D. degree in electrical engineering from the University of Ottawa, ON, Canada, in 1961, and an honorary doctorate from the Technical University of Budapest, Budapest, Hungary, in 1991. He held academic positions at the Technical University of Budapest, Stanford University and the University of California at Los Angeles. He worked in industry at Northern Electric R&D Laboratories and at Ampex Corp. He is now a Professor in the School of Electrical Engineering and Computer Science at Oregon State University.

Dr. Temes received the IEEE Leon K. Kirchmayer Graduate Teaching Award in 1998, and the IEEE Millennium Medal in 2000. He was the 2006 recipient of the IEEE Gustav Robert Kirchhoff Award, and the 2009 IEEE CAS Mac Valkenburg Award. He received the 2017 Semiconductor Industry Association-SRC University Researcher Award. He is a member of the National Academy of Engineering.

For more information, contact Prof. Sudhakar Pamarti (spamarti@ee.ucla.edu)

Date/Time:
Date(s) - Feb 14, 2019
2:00 pm - 3:00 pm

Location:
EE-IV Shannon Room #54-134
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095