A High-Performance and Energy-Efficient Decoder for Non-Binary LDPC Codes

Speaker: Yuta Toriyama
Affiliation: Ph.D. Candidate - UCLA

Abstract:  Binary Low-Density Parity-Check (LDPC) codes are a type of error correction code known to exhibit excellent error-correcting capabilities, and have increasingly been applied as the forward error correction solution in a multitude of systems and standards. In the pursuit of codes with higher coding gain, non-binary LDPC (NB-LDPC) codes defined over a Galois field of order q have risen as a strong candidate. For codes defined with similar rate and length, NB-LDPC codes exhibit a significant coding gain improvement relative to that of their binary counterparts. Unfortunately, NB-LDPC codes are currently limited from practical application by the immense complexity of their decoding algorithms, because the improved error-rate performance of higher field orders comes at the cost of increasing decoding algorithm complexity. Currently available ASIC implementation solutions for NB-LDPC code decoders are simultaneously low in throughput and power-hungry, leading to a low energy efficiency.

We propose several techniques at the algorithm level as well as hardware architecture level in an attempt to bring NB-LDPC codes closer to practical deployment. On the algorithm side, we propose several algorithmic modifications and analyze the corresponding hardware cost alleviation as well as impact on coding gain. We also study the quantization scheme for NB-LDPC decoders, again in the context of both the hardware and coding gain impacts, and we propose a technique that enables a good tradeoff in this space. On the hardware side, we develop a FPGA-based NB-LDPC decoder platform for architecture prototyping as well as hardware acceleration of code evaluation via error rate simulations. We also discuss the architectural techniques and innovations corresponding to our proposed algorithm for optimization of the implementation. Finally, a proof-of-concept ASIC chip is realized that integrates many of the proposed techniques. We are able to achieve a 3.7x improvement in the information throughput and 23.8x improvement in the energy efficiency over prior state-of-the-art, without sacrificing the strong error correcting capabilities of the NB-LDPC code.

Biography:  Yuta Toriyama received the B.S. degree in Electrical Engineering and Computer Sciences from University of California, Berkeley in 2009 and the M.S. degree in Electrical Engineering from University of California, Los Angeles (UCLA) in 2011. He is currently a Ph.D. candidate at UCLA in the Department of Electrical Engineering. Yuta’s research interests include algorithm-, architecture-, and circuit-level optimizations of digital VLSI systems for area and energy efficiency. He is the recipient of the Broadcom Fellowship in 2013-2014 and UCLA EE Departmental Fellowship in 2009.

For more information, contact Prof. Dejan Markovic (dejan@ee.ucla.edu)

Date/Time:
Date(s) - Nov 21, 2016
2:00 pm - 4:00 pm

Location:
E-IV Faraday Room #67-124
420 Westwood Plaza - 6th Flr., Los Angeles CA 90095