A Low-Power 80-Gb/s PAM4 Transmitter

Speaker: Yikun Chang
Affiliation: Ph.D. Candidate - UCLA

Abstract:  With the recent surge in the demand for high data rates, communication over copper media faces new challenges. First, the limited bandwidth removes so much of the signal’s high-frequency energy that equalization and detection become very difficult. Second, the greater data rates in serial links inevitably translate to high power consumption. State-of-the-art transmitters operating in the range of tens of gigabits per second draw hundreds of milliwatts, underscoring the need for new circuit and architecture techniques that can ease the trade-off with speed.

With a two-fold reduction in bandwidth occupancy compared to non-return-to-zero data, the PAM4 data format allows significant speed improvement but also introduces other issues such as skew and linearity. This research introduces a number of novel ideas so as to achieve both a very high data rate and much lower power consumption compared to the state of the art. In particular, we propose a “latchless” serializer architecture, a charge-steering multiplexer, and a high-speed divide-by-two circuit that directly generates outputs with a 25% duty cycle. These techniques culminate in an 80-Gb/s PAM4 transmitter, including an on-chip phase-locked loop that draws only 44 mW in 45-nm CMOS technology.

Biography:  Yikun Chang received her B.S. in Microelectronics from Peking University, Beijing, China in 2013, and M.S. in Electrical Engineering from University of California, Los Angeles in 2015. She is now a Ph.D. candidate in the Circuits and Embedded Systems track. Her research interests lie in low-power techniques in wireline transceivers. She is a recipient of the Analog Devices Outstanding Student Designer Award in 2016.

For more information, contact Prof. Behzad Razavi ()

Date(s) - Feb 27, 2018
5:00 pm - 7:00 pm

E-IV Faraday Room #67-124
420 Westwood Plaza - 6th Flr., Los Angeles CA 90095