BEOL (Back End of the Line) Interconnect and Heterogeneous Integration Strategies to Continue Moore’s Law Scaling

Speaker: Dr. Lawrence Clevenger
Affiliation: IBM Senior Technical Staff Member

Center for Heterogeneous Integration and Performance Scaling / Seminar Series


As semiconductor technology nodes scale towards 3 nm, there are acute difficulties in achieving interconnect scaling due to dimensionality, design, performance and reliability issues, and due to novel device architectures. This talk will discuss the key interconnect scaling and packaging heterogenous integration strategies for future technology nodes. These strategies must be co-optimized to determine the overall best definition.

For future semiconductor nodes, the ability of optical patterning dimensions to support the required line pitches is in doubt. Some current design methodologies do not emphasize wiring track reduction or additional wiring levels. The BEOL resistance and capacitance is a significant portion of the parasitic degradation of overall technology performance. BEOL resistance does not scale, due to exponential increases in Cu resistivity not compensated by decreasing Cu diffusion barrier thicknesses. Challenges for BEOL capacitance include integration issues which drive the effective dielectric constant higher than the modeled values. BEOL reliability is challenged by operation voltage requirements and by novel device architectures which strain electromigration and dielectric breakdown performance.

To mitigate these challenges, design methodologies are decreasing the number of wiring tracks in standard cell libraries and increasing the wiring levels to improve both performance and density. EUV lithography is replacing optical lithography to enhance design and performance, requiring fewer design rule restrictions, improving patterning tolerances, and enabling bi-directional metal and process simplification. Hardware teams will implement novel processes to enable recovery of partial resistance/capacitance scaling, and to support the increasing demands on interconnect electromigration and time dependent dielectric breakdown reliability. These patterning and process improvements are needed to support novel device architectures in technologies such as scaled FinFET and Stacked-Si-Nanosheets.

To further mitigate challenges in interconnect scaling, heterogeneous integration of IP has been migrating from SoC (System on a Chip) to SIP (System in Package).  This change has challenges in using novel packaging techniques with high density interconnects to achieve enhanced functionality and improved bandwidth and latency.


Dr. Larry Clevenger is an internationally recognized leader in semiconductor technology – taking new products from innovation to definition to early production. He has defined eight generations of semiconductor technologies for IBM as a chip hardware lead architect. Dr. Clevenger’s area of excellence is optimizing the on- chip interconnect from silicon devices to semiconductor packaging substrates for performance, yield, and cost. He is a member of the IBM Academy of Technology and a life time IBM Master Inventor with 309 issued patents    and 110 publications. Dr. Clevenger has also been active in creating and teaching gender bias workshops in IBM Research. In the fall of 2016, Dr. Clevenger traveled to Morocco with the IBM Corporate Service Corps team focusing on creating an implementation plan for cognitive agriculture deployment of fertilizers in sub-Saharan Africa. Dr. Clevenger received a B.S. in Material Engineering from UCLA and a Ph.D. in Electronic Materials from MIT.

For more information, contact Prof. Subramanian Iyer ()

Date(s) - Jul 17, 2018
10:00 am - 11:00 am

E-IV Maxwell Room #57-124
420 Westwood Plaza - 5th Flr. , Los Angeles CA 90095