Constrained Coding to Mitigate Inter-cell Interference in Multi-level Flash Memories

Speaker: Paul H. Siegel
Affiliation: UC San Diego

Abstract: Information is represented in NAND flash memories by the voltage levels of floating-gate transistors, or cells, arranged in a two-dimensional array. Inter-cell interference (ICI) arises when cells programmed to a high level disturb nearby cells programmed to a low level. This phenomenon leads to errors when information is retrieved from the memory. Experimental error characterization provides considerable insight into the two-dimensional patterns of programmed cell levels that are most susceptible to ICI-induced errors. This knowledge can then be used as the basis for the design of constrained codes that eliminate or at least reduce the frequency of occurrence of these “bad” patterns.  In this talk, we discuss recently developed methods for designing constrained codes that mitigate two-dimensional ICI effects in multilevel flash memories. This discussion provides a framework for surveying the state-of-the-art in the theory and practice of constrained coding, including results both classical and modern.

Biography: Paul H. Siegel received the S.B. and Ph.D. degrees in mathematics from Massachusetts   Institute   of   Technology   (MIT), Cambridge, MA, USA, in 1975 and 1979, respectively.  He  held  a  Chaim  Weizmann  Postdoctoral Fellowship with  the  Courant  Institute,  New  York University,  New  York,  NY,  USA.  He was with the IBM Research Division, San Jose, CA, USA, from 1980 to 1995. He joined the Faculty with the University  of  California,  San  Diego,  CA,  USA, in  July 1995, where he is currently a Professor of Electrical and Computer Engineering in the Jacobs School of Engineering. He is affiliated with the Center for Magnetic Recording Research where he holds an Endowed Chair and served as Director from 2000 to 2011. His research interests include information theory and communications, particularly coding and modulation techniques, with applications to digital data storage and transmission. He was a Member of the Board of Governors of the IEEE Information Theory Society from 1991 to 1996 and again from 2009 to 2014. He served as Co-Guest Editor of the May 1991 Special Issue on “Coding for Storage Devices” of the IEEE TRANSACTIONS ON INFORMATION THEORY. He served the same Transactions as Associate Editor for Coding Techniques from 1992 to 1995, and as Editor-in-Chief from July 2001 to July 2004. He was also Co-Guest Editor of the May/September 2001 two-part issue on “The Turbo Principle: From Theory to Practice” and the February 2016 issue on “Recent Advances in Capacity Approaching Codes” of the IEEE JOURNAL ON SELECTED  AREAS  IN COMMUNICATIONS. He is a member of the National Academy of Engineering. He was the 2015 Padovani Lecturer of the IEEE Information Theory Society. He was the co-recipient of the 2007 Best Paper Award in Signal Processing and Coding for Data Storage from the Data Storage Technical Committee of the IEEE Communications Society. He was the co-recipient of the 1992 IEEE Information Theory Society Paper Award and the 1993 IEEE Communications Society Leonard G. Abraham Prize Paper Award.

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Date(s) - Feb 29, 2016
1:00 pm - 2:00 pm

EE-IV Shannon Room #54-134
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095