Doping Profile Engineering for Advanced Transistors

Speaker: Peng Lu
Affiliation: Ph.D. Candidate

Via Zoom Only:   https://ucla.zoom.us/j/92467367035

Abstract:   Over the last decades, conventional scaling (Moore’s law) has provided continuous improvement in semiconductor device/circuit technology. FinFETs, featuring superior electrostatic control compared to planer FETs, have been the mainstream technology for the front-end-of-line (FEoL) application since the 22-nm node. Process-induced performance variation, which is already a key limit in 7/10nm node FinFETs, is becoming even more severe in beyond 5-nm node. Furthermore, FinFETs’ analog/RF performances are inferior to those in bulk and SOI transistors, preventing their applications in the system on chip (SoC) designs. In this work, 3D source/drain extension (SDE) doping profile control technique, developed for DC performance enhancement in 7/10-nm node FinFET, is proposed as an effective method for variability suppression and DC/analog performance enhancement in 3-nm node. The methodology of 3D doping profile optimization and governing physics are systematically analyzed.

In addition to transistor scaling, wafer-level packaging (WLP) has also been widely accepted as a pathway to further increase the device density. Active device integration in the back-end-of-line (BEoL) has been proposed to enhance the interconnect bandwidth, design flexibility, and reduce power consumption. Multi-layered molybdenum disulfide (MoS₂), featuring a finite bandgap, high mobility, and possible CMOS BEoL compatible (<400 °C) synthesis process, is a promising candidate for such an application. One of the major roadblocks in MoS₂ FET’s fabrication is the lack of the controllable doping process for S/D formation. This work demonstrates a carrier control technique in MoS₂ by introducing substitutional Nb. The impact of high concentration Nb is quantified to precisely modulate the carrier density. Electrical characterizations show that a high carrier density (>2×10²⁰ cm^-3) can be achieved, favorable for S/D formation with low access resistance. The relations between high concentration Nb and mobility, contact resistivity, and bandgap are also analyzed to guide MoS₂ transistor design.

Biography: Peng Lu is currently a PhD candidate in the ECE Department at UCLA. He received the B.S. degree in school of electronics & electrical engineering from University of Glasgow in 2012, and M.S. degree in ECE Department, UCLA in 2014, respectively.  His current research interests include  variability analysis and design optimization for advanced VLSI transistor.

For more information, contact Prof. Jason Woo (woo@ee.ucla.edu)

Date/Time:
Date(s) - May 04, 2020
10:00 am - 12:00 pm

Location:
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