High-Speed Time-Interleaved ADC for Wireless and Wireline Applications

Speaker: Xiao Wang
Affiliation: Ph.D. Candidate - UCLA

Abstract:  The emerging applications such as Internet-of-Things (IoT), self-driven car and artificial intelligence (AI) trigger rapid increase in bandwidth demand in data centers and telecommunication infrastructure. The data traffic in global network is expected to be tripled by 2020 and the ITRS predicts the IO speed to exceed 60 GB/s in 2020. ADC-based backplane receivers and coherent fiber-optical receivers are promising technologies for the next generation wireline communication systems. For both technologies, high speed analog-to-digital converter (ADC) of over multi GS/s is one key enabler. For 5G wireless communication system high resolution ADC (>7bit) with sampling speed over 1GHz is required. Many other applications also demand ADC with performance that has never been achieved before while only provides a strict power budget. To achieve sufficient bandwidth and linearity, track-and-hold (T&H) buffers are usually employed before and/or after the sampling switches in TI ADCs. This dissertation introduces two different methods to deal with stringent linearity/bandwidth requirements and avoid mismatches without using complex digital calibrations. Two fabricated chips 8b 2-GS/s and 8b 8.8-GS/s will be shown as the silicon verification of the proposed methods.

First, we introduce an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC. A two-level 2×8 master-slave hierarchical interleaved architecture is employed. A complementary dual-loop-assisted buffer is proposed to achieve both high linearity and bandwidth with low power. This time-interleaved ADC achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers.

Second, we report a time-interleaved two-step ADC architecture built upon a new concept of virtual-ground sampling and using merged front-end T/H with residue generation, input termination and buffering, aimed to push effective-number-of-bits (ENOB) of time-interleaved ADCs from a current 5~6b range to 7~9b level without degrading conversion rates. The new ADC architecture is validated using a 2-GS/s 8b ADC fabricated in foundry 28-nm CMOS, achieving 43-dB SNDR and 55-dB SFDR up to Nyquist frequency.

Biography: Xiao Wang is currently a Ph.D. candidate in the Department of Electrical and Computer Engineering under the mentorship of Professor Frank Chang. He received M.S. degree from UCSB in 2013, and B.S. Degree from University of Electronic Science and Technology of China in 2011.

For more information, contact Prof. Frank Chang ()

Date/Time:
Date(s) - Apr 04, 2018
1:00 pm - 3:00 pm

Location:
E-IV Maxwell Room #57-124
420 Westwood Plaza - 5th Flr. , Los Angeles CA 90095