Holistic Energy-Efficient Design in Optical Interconnects

Speaker: Prof. Azita Emami
Affiliation: Caltech

Abstract: The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Communication is a necessary adjunct to computation, and whether in the context of high-performance computing, mobile devices or biomedical implants, chip-to-chip communication can take up a significant portion of the overall system power budget. Today Data Center and High Performance Computing (HPC) performance is increasingly limited by interconnection bandwidth. Maintaining continued aggregate bandwidth growth without overwhelming the power budget for these large scale computing systems and data centers is paramount. The historic power efficiency gains via CMOS technology scaling for such interconnects have rolled off over the past decade, and new low-cost approaches are necessary. In this talk a number of promising solutions including Silicon-Photonic-based interconnects that can overcome these challenges will be discussed. In particular effective co-design of electronics and photonics as a holistic approach for reducing the total power consumption and enhancing the performance of the link will be presented.

Biography: Azita Emami received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1999 and 2004 respectively. She received her B.S. degree from Sharif University of Technology in 1996. Professor Emami joined IBM T. J. Watson Research Center in 2004 as a research staff member in the Communication Technologies Department. From Fall 2006 to Summer 2007, she was an Assistant Professor of Electrical Engineering at Columbia University in the city of New York. In 2007, she joined Caltech, where she is now a Professor of Electrical Engineering and Medical Engineering. She also serves as the deputy chair of division of Engineering and Applied Sciences at Caltech. Her current research interests include mixed-signal integrated circuits and systems, high-speed on-chip and chip-to-chip interconnects, system and circuit design solutions for highly-scaled CMOS technologies, wearable and implantable devices for neural recording, stimulation, and efficient drug delivery.

For more information contact Professor Behzad Razavi ()

Date/Time:
Date(s) - May 23, 2016
1:00 pm - 2:00 pm

Location:
EE-IV Shannon Room #54-134
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095