# p-bits and p-circuits for Probabilistic Spin Logic

**Speaker:** Kerem Y. Camsari
**Affiliation:** University of Purdue

**Abstract:** In this talk, I will present our recent on work on Probabilistic Spin Logic [1], based on probabilistic bits (*p*-bits) that fluctuate stochastically between “0” and “1”. We have shown that* p*-circuits built out of *p*-bits can provide a viable hardware framework for “Ising computing” [2], Bayesian Networks [3], machine learning algorithms such as Boltzmann Machines for image recognition [4] and a special kind of Boolean logic that is *invertible*. An invertible Boolean circuit not only provides the output for given inputs but also all inputs consistent with a given output. This special property can be useful in tackling hard problems, such as the subset sum problem and prime factorization.

I will show that *p*-bits can be compactly implemented by the existing Embedded Magnetic Tunnel Junction devices [5] that have been rising as a memory technology, making* p*-bits particularly relevant to spintronics, although we have explored non-magnetic implementations of *p*-bits as well [6,7].

I will briefly talk about a modular, physics-based circuit framework that combines a wide range of emerging materials and phenomena in spintronics and magnetism [8] and how we have used this framework from understanding experiments to evaluating *p*-bits and *p*-circuits. I will argue that such an *Atoms* to Systems approach is essential in the search for energy-efficient *hardware accelerators* for applications in machine learning algorithms in a beyond-Moore era of electronics.

[1] K.Y. Camsari, R. Faria, B. M. Sutton and S. Datta, “Stochastic *p*-bits for Invertible Boolean Logic,” Phys. Rev. X, 3, 031014 (2017).

[2] B.M. Sutton, K.Y. Camsari, B. Behin-Aein and S. Datta “Intrinsic optimization using stochastic nanomagnets”, Scientific Reports, 7, 44370 (2017).

[3] R. Faria, K. Y. Camsari, and S. Datta. “Implementing Bayesian Networks with Embedded Stochastic MRAM.” AIP Advances, (2018).

[4] R. Zand, K. Y. Camsari, I. Ahmed, S. D. Pyle, C. H. Kim, R. F. DeMara, “Low-Energy Deep Belief Networks Enabled by Near-Zero Energy Barrier Spintronic Devices”, GLSVLSI (2018).

[5] K. Y. Camsari, S. Salahuddin, S. Datta, “Implementing *p*-bits with Embedded MTJ”, IEEE Electron Device Letters, 38 (12), 1767-1770 (2017).

[6] A. Z. Pervaiz, L. A. Ghantasala, K. Y. Camsari and S. Datta, “Hardware emulation of stochastic *p*-bits for invertible logic”, Scientific Reports, 7, 10994 (2017).

[7] A. Z. Pervaiz, B. M. Sutton, L. A. Ghantasala, K. Y. Camsari. Weighted* p*-bits for FPGA implementation of probabilistic circuits. arXiv:1712.04166. (2017).

[8] K. Y. Camsari, S. Ganguly and S. Datta, “Modular Approach to Spintronics”, Scientific Reports, 5, 10571 (2015).

**Biography:** Kerem Y. Camsari is a post-doctoral researcher at the School of Electrical and Computer Engineering at Purdue University working with the Supriyo Datta group where he also received his PhD degree in 2015. His PhD thesis established the “Modular Approach to Spintronics”, bringing a wide range of physical methods for combining transport and magnetization dynamics into a unified circuit framework. His postdoctoral work has been on Probabilistic Spin Logic (PSL), a computational framework based on probabilistic bits (p-bit) and p-circuits that can be efficient hardware accelerators for a wide range of problems in machine learning and optimization.

For more information, contact Prof. Yuanxun “Ethan” Wang ()

**Date/Time:**

Date(s) - Apr 23, 2018*12:30 pm - 1:30 pm*

**Location:**

EE-IV Shannon Room #54-134

420 Westwood Plaza - 5th Flr., Los Angeles CA 90095