Intel Corp. – Physical Design Engineer position

Physical Design Engineer – 782213

Description

Our team is involved in layout synthesis customized for Intel process technology. Responsibilities for a successful candidate: creates bottoms-up elements of chip design including but not limited to FET, cell, and block-level custom layouts, auto-place and route algorithms, floor planning, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Executes and verifies complex layout development and execution of project methodologies and/or flow developments.

Requires expansive knowledge and practical application of methodologies and physical design.

The ideal candidate should exhibit the following behavioral traits:

·         enjoy solving complex spatial puzzles.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

The candidate must possess a Master and/or PhD degree in CS, Math, CE, EE, or a related field.

Candidate must have 6 + months of work or educational experience in the following:

·         good at math, specifically in geometry.

·         expert programmer, preferably in C++ or Python, Ruby, Haskell, Tcl.

Preferred Qualifications:

·         Discrete math knowledge

·         Functional programming (Haskell)

Primary Location

USA-Oregon, Hillsboro

Business Group

As the world’s largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art — from semiconductor process development and manufacturing, through yield improvement to final test and optimization, and lastly packaging. Employees in the Technology and Manufacturing group are part of a worldwide network of manufacturing and assembly/test facilities. Our team is involved in solving very challenging aspects of Moore’s law (i.e. doubling the number of transistors every two years). Moore’s law puts tremendous pressure and challenge on the way we manufacture, model and create physical layout that is done on time, with high yield.