Publications, Seminars, and Patents

(Note: Copyrights may have been transferred to the appropriate publishers. Reprints are provided here for personal use only.)

Keynote Lectures

  1. C. O. Chui, "High Mobility Nanoelectronic Devices, Physics, and Technology," Proc. 7th Int. Symp. Adv. Fluid Inf. and 4th Int. Symp. Transdiscipl. Fluid Integrat., pp. 84-91, Institute of Fluid Science, Tohoku University, Sendai, Japan, December 15, 2007.

Review Papers

  1. C. O. Chui, H. Kim, D. Chi, P. C. McIntyre, and K. C. Saraswat, "Nanoscale Germanium MOS Dielectrics―Part II: High-k Gate Dielectrics," IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1509-1516, 2006.
  2. C. O. Chui, F. Ito, and K. C. Saraswat, "Nanoscale Germanium MOS Dielectrics―Part I: Germanium Oxynitrides," IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1501-1508, 2006.

Invited Papers

  1. C. O. Chui, K.-H. Shih, and K. Shoorideh, "Low Dissipation Nanoscale Transistor Physics and Operations," Proc. 9th Int. Conf. on Solid-State and Integr. Circuit Technol. (ICSICT), Paper A1.3, pp. 29-32, Beijing, People's Republic of China, October 20-23, 2008.
  2. K. C. Saraswat, C. O. Chui, T. Krishnamohan, D. Kim, A. Nayfeh, and A. Pethe, "High Performance Germanium MOSFETs," Mater. Sci. Eng. B, vol. 135, no. 3, pp. 242-249, 2006.
  3. K. C. Saraswat, C. O. Chui, D. Kim, T. Krishnamohan, and A. Pethe, "High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 25.2, pp. 659-662, San Francisco, CA, December 11-13, 2006.
  4. P. C. McIntyre, D. Chi, C. O. Chui, H. Kim, K.-I. Seo, K. C. Saraswat, R. Sreenivasan, T. Sugawara, F. S. Aguirre-Testado, and R. M. Wallace, "Interface Layers for High-k/Ge Gate Stacks: Are They Necessary?" Electrochem. Soc. Trans., vol. 3, no. 7, pp. 519-530, 2006.
  5. P. C. McIntyre, D. Chi, C. O. Chui, H. Kim, K. I. Seo, and K. C. Saraswat, "Interface Layers for High-k/Ge Gate Stacks: Are They Necessary?" Proc. 210th Mtg. Electrochem. Soc., Paper E13-1456, Cancun, Mexico, October 29-November 3, 2006.
  6. K. C. Saraswat, C. O. Chui, P. Kapur, T. Krishnamohan, A. Nayfeh, A. K. Okyay, and R. S. Shenoy, "Performance Limitations of Si CMOS and Alternatives for Nanoelectronics," Int. J. of High-Speed Electronics and Syst., vol. 16, no. 1, pp. 175-192, 2006.
  7. C. O. Chui and K. C. Saraswat, "Advanced Germanium MOS Devices and Technology," The 2005 IEEE Int. Conf. on Electron Dev. and Solid-State Circuits (EDSSC) Tech. Dig., pp. 101-106, Hong Kong, People's Republic of China, December 19-21, 2005.
  8. K. C. Saraswat, A. Nayfeh, and C. O. Chui, "Gate Dielectrics for Ge MOS Technology," Proc. 208th Mtg. Electrochem. Soc., Paper G3-0489, Los Angeles, CA, October 16-21, 2005.
  9. K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. Nayfeh, and P. McIntyre, "Ge Based High Performance Nanoscale MOSFETs," Microelectron. Eng., vol. 80, pp. 15-21, 2005.
  10. K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. Nayfeh, and P. McIntyre, "Ge Based High Performance Nanoscale MOSFETs," The 14th Bi-annual Conf. on Insulating Films on Semicond. (INFOS), Leuven, Belgium, June 22-24, 2005.
  11. K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. Nayfeh, and P. McIntyre, "Ge Based High Performance Nanoscale MOSFETs," Proc. 2005 Mater. Res. Soc. Spr. Mtg., Symp. Transistor Processing and Characterization-II, Paper G14.1, San Francisco, CA, March 28-April 1, 2005.
  12. K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. Nayfeh, and R. S. Shenoy, "Performance Limitations of Si CMOS and Alternatives for Nanoelectronics," SEMI-ECS 2005 Int. Semicond. Technol. Conf. (ISTC), Shanghai, People's Republic of China, March 15-17, 2005.
  13. K. C. Saraswat, C. O. Chui, A. Nayfeh, H. Kim, A. K. Okyay, and P. C. McIntyre, "Ge Based High Performance Nanoscale MOSFETs and Integrated Optical Interconnects," SEMICON Korea, Seoul, South Korea, February 2-4, 2005.
  14. P. C. McIntyre, H. Kim, K.-I. Seo, C. O. Chui, B. B. Triplett, D.-I. Lee, P. Pianetta, S. Stemmer, and K. C. Saraswat, "Interface Engineering for High-k/Si and High-k/Ge Structures," Proc. 10th Wrkshp. on Formation, Characterization and Reliability of Ultrathin Silicon Oxides, Mishima, Japan, January 28-29, 2005.
  15. K. C. Saraswat, C. O. Chui, P. Kapur, T. Krishnamohan, A. Nayfeh, A. K. Okyay, and R. S. Shenoy, "Performance Limitations of Devices and Interconnects and Possible Alternatives for Nanoelectronics," Proc. 2004 Adv. Wrkshp. on ‘Frontiers in Electronics’ (WOFE), Palm Beach, Aruba, December 18-22, 2004.
  16. K. C. Saraswat, C. O. Chui, A. Nayfeh, H. Kim, and P. McIntyre, "Ge Surface Passivation for High Performance MOSFETs," The 35th IEEE Semicond. Interface Specialists Conf. (SISC) Tech. Dig., San Diego, CA, December 9-11, 2004.
  17. K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. K. Okyay, H. Kim, and P. McIntyre, "Ge and SiGe for High Performance MOSFETs and Integrated Optical Interconnects," The 2004 Int. Conf. on Solid State Dev. Mater. (SSDM) Tech. Dig., Tokyo, Japan, September 14-17, 2004.
  18. C. O. Chui and K. C. Saraswat, "Advanced Germanium MOSFET Technologies with High-k Gate Dielectrics and Shallow Junctions," The 2004 IEEE Int. Conf. on Integr. Circuit Design and Technol. (ICICDT) Tech. Dig., Paper H2, pp. 245-252, Austin, TX, May 17-19, 2004.
  19. C. O. Chui and K. C. Saraswat, "Low Thermal Budget Ge MOS Technology," Proc. 205th Mtg. of Electrochem. Soc., Paper G1-254, San Antonio, TX, May 9-14, 2004.
  20. P. McIntyre, H. Kim, D. Chi, C. O. Chui, B. Triplett, A. Javey, H. Dai, and K. Saraswat, "Novel Deposition Processes for High-k/Ge Devices: Interface Engineering," Proc. 2004 Mater. Res. Soc. Spr. Mtg., Symp. High-k and High Mobility Substrates, Paper B5.1/D5.1, San Francisco, CA, April 12-16, 2004.
  21. K. C. Saraswat, C. O. Chui, P. C. McIntyre, and B. B. Triplett, "Novel Germanium Technology and Devices for High Performance MOSFETs and Integrated On-Chip Optical Clocking," Proc. 203rd Mtg. Electrochem. Soc., Paper G1-455, Paris, France, April 27-May 2, 2003.

Journal Papers

  1. P. T. Chen, Y. Sun, E. Kim, P. C. McIntyre, W. Tsai, M. Garner, P. Pianetta, Y. Nishi, and C. O. Chui, "HfO2 Gate Dielectric on (NH4)2S Passivated (100) GaAs Grown by Atomic Layer Deposition," J. Appl. Phys., vol. 103, art. 034106, 2008.
  2. K. Martens, C. O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. M. Heyns, T. Krishnamohan, K. C. Saraswat, H. E. Maes, and G. Groeseneken, "On the Correct Extraction of Interface Trap Density of MOS Devices with High-Mobility Semiconductor Substrates," IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 547-556, 2008.
  3. N. Goel, P. Majhi, C. O. Chui, W. Tsai, D. Choi, and J. S. Harris, "InGaAs Metal-Oxide-Semiconductor Capacitors with HfO2 Gate Dielectric Grown by Atomic-Layer Deposition," Appl. Phys. Lett., vol. 89, art. 163517, 2006.
  4. H. Lan, T. W. Chen, C. O. Chui, P. Nikaeen, J. W. Kim, and R. W. Dutton, "Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs," IEEE J. of Solid-State Circuits (Special Issue on the IEEE 2005 Custom Integr. Circuit Conf.), vol. 41, no. 8, pp. 1817-1829, 2006.
  5. A. K. Okyay, C. O. Chui, and K. C. Sarawat, "Leakage Suppression by Asymmetric Area Electrodes in Metal-Semiconductor-Metal Photodetectors," Appl. Phys. Lett., vol. 88, art. 063505, 2006.
  6. C. O. Chui, L. Kulig, J. Moran, W. Tsai, and K. C. Saraswat, "Germanium n-Type Shallow Junction Activation Dependences," Appl. Phys. Lett., vol. 87, art. 091909, 2005.
  7. C.-H. Lu, G. M. T. Wong, M. D. Deal, W. Tsai, P. Majhi, C. O. Chui, M. R. Visokay, J. J. Chambers, L. Colombo, B. M. Clemens, and Y. Nishi, "Characteristics and Mechanism of Tunable Work Function Gate Electrodes Using a Bilayer Metal Structure on SiO2 and HfO2," IEEE Electron Device Lett., vol. 26, no. 7, pp. 445-447, 2005.
  8. C. O. Chui, D.-I. Lee, A. A. Singh, P. A. Pianetta, and K. C. Saraswat, "Zirconia-Germanium Interface Photoemission Spectroscopy Using Synchrotron Radiation," J. Appl. Phys., vol. 97, art. 113518, 2005.
  9. A. Nayfeh, C. O. Chui, T. Yonehara, and K. C. Saraswat, "Fabrication of High-Quality p-MOSFET in Ge Grown Heteroepitaxially on Si," IEEE Electron Device Lett., vol. 26, no. 5, pp. 311-313, 2005.
  10. H. Kim, P. C. McIntyre, C. O. Chui, K. C. Saraswat, and M.-H. Cho, "Interfacial Characteristics of HfO2 Grown on Nitrided Ge (100) Substrates by Atomic-Layer Deposition," Appl. Phys. Lett., vol. 85, no. 14, pp. 2902-2904, 2004.
  11. A. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, "Effects of Hydrogen Annealing on Heteroepitaxial-Ge Layers on Si: Surface Roughness and Electrical Quality," Appl. Phys. Lett., vol. 85, no. 14, pp. 2815-2817, 2004.
  12. H. Kim, P. C. McIntyre, C. O. Chui, K. C. Saraswat, and S. Stemmer, "Engineering Chemically Abrupt High-k Metal Oxide/Silicon Interfaces Using An Oxygen-Gettering Metal Overlayer," J. Appl. Phys., vol. 96, no. 6, pp. 3467-3472, 2004.
  13. C. O. Chui, F. Ito, and K. C. Saraswat, "Scalability and Electrical Properties of Germanium Oxynitride MOS Dielectrics," IEEE Electron Device Lett., vol. 25, no. 9, pp. 613-615, 2004.
  14. M. S. Bakir, C. O. Chui, A. K. Okyay, K. C. Saraswat, and J. D. Meindl, "Integration of Optical Polymer Pillars Chip I/O Interconnections with Si MSM Photodetectors," IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1084-1090, 2004.
  15. D. Chi, C. O. Chui, K. C. Saraswat, B. B. Triplett, and P. C. McIntyre, "Zirconia Grown by Ultraviolet Ozone Oxidation on Germanium (100) Substrates," J. Appl. Phys., vol. 96, no. 1, pp. 813-819, 2004.
  16. C. O. Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, "Atomic Layer Deposition of High-k Dielectric for Germanium MOS Applications―Substrate Surface Preparation," IEEE Electron Device Lett., vol. 25, no. 5, pp. 274-276, 2004.
  17. C. O. Chui, A. K. Okyay, and K. C. Saraswat, "Effective Dark Current Suppression with Asymmetric MSM Photodetectors in Group IV Semiconductors," IEEE Photon. Technol. Lett., vol. 15, no. 11, pp. 1585-1587, 2003.
  18. C. O. Chui, K. Gopalakrishnan, P. B. Griffin, J. D. Plummer, and K. C. Saraswat, "Activation and Diffusion Studies of Ion-Implanted p and n Dopants in Germanium," Appl. Phys. Lett., vol. 83, no. 16, pp. 3275-3277, 2003.
  19. H. Kim, C. O. Chui, K. C. Saraswat, and P. C. McIntyre, "Local Epitaxial Growth of ZrO2 on Ge (100) Substrates by Atomic Layer Epitaxy," Appl. Phys. Lett., vol. 83, no. 13, pp. 2647-2649, 2003.
  20. C. O. Chui, S. Ramanathan, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "Germanium MOS Capacitors Incorporating Ultrathin High-k Gate Dielectric," IEEE Electron Device Lett., vol. 23, no. 8, pp. 473-475, 2002.

Conference Papers

  1. K.-H. Shih and C. O. Chui, "The Low Subthreshold Swing Possibility with Asymmetries in Double-Gate SOI MOSFET," Proc. 2008 IEEE Int. SOI Conf., pp. 53-54, New Paltz, NY, October 6-9, 2008.
  2. D. Choi, M. Warusawithana, C. O. Chui, J. Chen, W. Tsai, D. G. Schlom, and J. S. Harris, "The Electrical Characterization of Molecular-Beam-Deposited LaAlO3 on GaAs and Its Annealing Effects," Mater. Res. Soc. Symp. Proc., vol. 996, Paper H5.31, 2007.
  3. D. Choi, M. Warusawithana, C. O. Chui, N. Goel, W. Tsai, D. G. Schlom, and J. S. Harris, "Surface Reconstruction Dependence and Annealing of Amorphous Lanthanum Aluminate on GaAs," Proc. 2007 Mater. Res. Soc. Spr. Mtg., Symp. High-k Dielectrics/Semiconductor Interfaces, Paper H5.31, San Francisco, CA, April 9-13, 2007.
  4. P.-T. J. Chen, Y. Sun, C. O. Chui, E. Kim, M. Garner, P. Pianetta, N. Goel, W. Tsai, P. McIntyre, and Y. Nishi, "Interface Analysis Between ALD High-k HfO2 and Sulfur Passivated GaAs," Proc. 2007 Mater. Res. Soc. Spr. Mtg., Symp. High-k Interfaces: High Mobility Substrates and Metal Electrodes, Paper H4.3, San Francisco, CA, April 9-13, 2007.
  5. E. Kim, J. Chen, D. Choi, N. Goel, C. O. Chui, W. Tsai, J. Harris, Y. Nishi, K. Saraswat, and P. C. McIntyre, "Electrical and Physical Characterization of ALD-Grown HfO2 Gate Dielectrics on GaAs (100) Substates with Sulfur Passivation," Proc. 2007 Mater. Res. Soc. Spr. Mtg., Symp. Extending Moore's Law with Advanced Channel Materials, Paper G5.12, San Francisco, CA, April 9-13, 2007.
  6. T. J. Grassman, S. R. Bishop, A. C. Kummel, C. O. Chui, and W. Tsai, "Comparison of ZrO2/Ge(100) and HfO2/Ge(100) Bonding and Electronic Structure," The 37th IEEE Semicond. Interface Specialists Conf. (SISC) Techn. Dig., San Diego, CA, December 7-9, 2006.
  7. K. Shin, C. O. Chui, and T.-J. King, "Dual Stress Capping Layer Enhancement Study for Hybrid Orientation FinFET CMOS Technology," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 39.6, pp. 1009-1012, Washington, DC, December 5-7, 2005.
  8. H. Lan, T. W. Chen, C. O. Chui, P. Nikaeen, J. W. Kim, and R. W. Dutton, "Synthesized Compact Model and Experimental Results for Substrate Noise Coupling in Lightly Doped Processes," Proc. IEEE Custom Integr. Circuit Conf. (CICC), Paper 13-4, pp. 469-472, San Jose, CA, September 18-21, 2005.
  9. A. Nayfeh, C. O. Chui, T. Yonehara, and K. C. Saraswat, "High Mobility Ge pMOS Fabricated Using a Novel Heteroepitaxial Ge on Si Growth Method," IEEE 63rd Annual Dev. Res. Conf. (DRC) Dig., Paper III-18, pp. 89-90, Santa Barbara, CA, June 20-22, 2005.
  10. A. K. Okyay, C. O. Chui, and K. C. Saraswat, "A Novel Technique to Reduce Leakage in Metal-Semiconductor-Metal Photodetectors," IEEE 63rd Annual Dev. Res. Conf. (DRC) Dig., Paper III-8, pp. 69-70, Santa Barbara, CA, June 20-22, 2005.
  11. A. M. Nayfeh, C. O. Chui, T. Yonehara, and K. Saraswat, "High Quality Heteroepitaxial-Ge Layers on Si by Multi-Step Hydrogen Annealing and Re-Growth," Proc. 2005 Mater. Res. Soc. Spr. Mtg., Symp. Physical and Electrical Characterization-I, Paper G8.4, San Francisco, CA, March 28-April 1, 2005.
  12. A. K. Okyay, C. O. Chui, M. S. Bakir, J. D. Meindl, and K. C. Saraswat, "Integration of Polymer Pillar Optical Interconnects with Group IV MSM Photodetectors," Proc. 2005 Mater. Res. Soc. Spr. Mtg., Symp. Photonic Systems, Paper D4.1, San Francisco, CA, March 28-April 1, 2005.
  13. C. O. Chui, L. Kulig, J. Moran, W. Tsai, and K. C. Saraswat, "A Reason for Poor Ge n-MOSFET Performance: Source/Drain Junction Dose-Dependent Activation," Proc. 2005 Mater. Res. Soc. Spr. Mtg., Symp. Transistor Processing and Characterization-I, Paper G7.3, San Francisco, CA, March 28-April 1, 2005.
  14. E. Pop, C. O. Chui, S. Sinha, R. Dutton, and K. Goodson, "Electro-Thermal Comparison and Performance Optimization of Thin-Body SOI and GOI MOSFETs," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 16.6, pp. 411-414, San Francisco, CA, December 13-15, 2004.
  15. H. Lan, T. W. Chen, C. O. Chui, and R. W. Dutton, "Compact Modeling and Experimental Verification of Substrate Resistance in Lightly Doped Substrates," Proc. 12th Wrkshp. on Syn. and Syst. Integrat. of Mixed Inf. Technol. (SASIMI), pp. 189-195, Kanazawa, Japan, October 18-19, 2004.
  16. A. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, "Effects of Hydrogen Annealing on Heteroepitaxial-Ge Layers on Si: Surface Roughness and Electrical Quality," Proc. 206th Mtg. Electrochem. Soc., Paper M2-1403, Honolulu, HI, October 3-8, 2004.
  17. H. Kim, P. C. McIntyre, C. O. Chui, K. Saraswat, and S. Stemmer, "Engineering Chemically Abrupt High-k Metal Oxide/Silicon Interfaces Using Oxygen-Gettering Metal Overlayers," The 13th Wrkshp. Dielectrics in Microelectronics (WoDiM 2004), Paper 4a-2, Kinsale, Ireland, June 28-30, 2004. (BEST PAPER AWARD)
  18. H. Kim, P. C. McIntyre, S. Stemmer, C. O. Chui, and K. C. Saraswat, "High-k Interface Engineering: the Interaction of Reactive Metal Electrodes with ALD-ZrO2/SiO2 and HfO2/SiO2 Gate Stacks," Proc. 2004 Mater. Res. Soc. Spr. Mtg., Symp. Metal Gates, Paper D4.4, San Francisco, CA, April 12-16, 2004.
  19. C. O. Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, "Ge MOS Dielectric Stack with ALD High-k Metal Oxide and Oxynitride Interlayer," Proc. 2004 Mater. Res. Soc. Spr. Mtg., Symp. High-Mobility Group-IV Mat. Dev., Paper B8.7, San Francisco, CA, April 12-16, 2004.
  20. D. Chi, C. O. Chui, S. Ramanathan, B. Triplett, K. C. Saraswat, and P. C. McIntyre, "Metal Oxide/Semiconductor Interfaces in UV-Ozone Oxidized High-k Dielectric Stacks on Si and Ge (001) Substrates," Proc. 2004 Mater. Res. Soc. Spr. Mtg., Symp. High-k and High Mobility Substrates, Paper B5.6/D5.6, San Francisco, CA, April 12-16, 2004.
  21. C. O. Chui, D.-I. Lee, A. A. Singh, D. Chi, P. C. McIntyre, P. A. Pianetta, and K. C. Saraswat, "Synchrotron Radiation Photoemission Spectroscopy of High-k Gate Stack in High-Performance Ge MOS Devices," Proc. 2004 Mater. Res. Soc. Spr. Mtg., Symp. High-k and High Mobility Substrates, Paper B5.2/D5.2, San Francisco, CA, April 12-16, 2004.
  22. C. O. Chui, H. Kim, J. P. McVittie, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "A Novel Self-Aligned Gate-Last MOSFET Process Comparing the High-k Candidates," IEEE 2003 Int. Semicond. Dev. Res. Symp. (ISDRS) Proc., Paper FA6-05, pp. 464-465, Washington, DC, December 10-12, 2003.
  23. C. O. Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, "A Germanium NMOSFET Process Integrating Metal Gate and Improved Hi-k Dielectrics," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 18.3, pp. 437-440, Washington, DC, December 7-10, 2003.
  24. D. Chi, C. O. Chui, S. Ramanathan, B. B. Triplett, K. C. Saraswat, and P. C. McIntyre, "UV-Ozone Oxidized High-k Dielectrics on Si and Ge Substrates," The 45th TMS Electronic Mater. Conf. (EMC) Dig., Paper S5, Salt Lake City, UT, June 25-27, 2003.
  25. A. K. Okyay, C. O. Chui, and K. C. Saraswat, "Asymmetric Group IV MSM Photodetectors with Reduced Dark Currents," IEEE Conf. Lasers and Electro-Optics (CLEO) Tech. Dig., Paper CTuD4, pp. 464-466, Baltimore, MD, June 3-5, 2003.
  26. D. Chi, B. B. Triplett, P. C. McIntyre, C. O. Chui, K. C. Saraswat, E. Garfunkel, and T. Gustafsson, "High-k Metal Oxides Dielectrics on Ge (100) Substrates," Proc. 2003 Mater. Res. Soc. Spr. Mtg., Symp. Advanced Gate Stack Materials, Paper D3.17, San Francisco, CA, April 21-25, 2003.
  27. H. Kim, P. C. McIntyre, C. O. Chui, and K. C. Saraswat, "Atomic Layer Deposition of ZrO2 on Si and Ge Substrate," Proc. 2003 Mater. Res. Soc. Spr. Mtg., Symp. High-k Dielectrics, Paper D2.11, San Francisco, CA, April 21-25, 2003.
  28. C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "A Sub-400ºC Germanium MOSFET Technology with High-k Dielectric and Metal Gate," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 17.3, pp. 437-440, San Francisco, CA, December 8-11, 2002.
  29. C. O. Chui, S. Ramanathan, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "Ultrathin High-k Gate Dielectric Technology for Germanium MOS Applications," IEEE 60th Annual Dev. Res. Conf. (DRC) Dig., Paper VII.B-2, pp. 191-192, Santa Barbara, CA, June 24-26, 2002. (BEST STUDENT PAPER AWARD)
  30. C. O. Chui and K. C. Saraswat, "Germanium Damascene Process by Selective LPCVD and Surface Smoothening Technique," Proc. 2002 Mater. Res. Soc. Spr. Mtg., Symp. Growth: New Methods and Fundamentals, Paper A19.5, San Francisco, CA, April 1-5, 2002.
  31. T.-Y. Chiang, S. J. Souri, C. O. Chui, and K. C. Saraswat, "Thermal Analysis of Heterogeneous 3-D ICs with Various Integration Scenarios," IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig., Paper 31.2, pp. 681-684, Washington, DC, December 2-5, 2001.

Book Chapters

     4.     C. O. Chui and K. C. Saraswat, "Germanium Nanodevices and Technology," Advanced Gate Stacks for High-Mobility Semiconductors (edited by A. Dimoulas, E. Gusev, P. McIntyre, and M. Heyns), Springer-Verlag, New York, December 2007.
     3.     C. O. Chui and K. C. Saraswat, "Advances Germanium MOS Devices," Germanium-Based Technologies: From Materials to Devices (edited by C. Claeys and E. Simoen), Elsevier Science, Amsterdam, May 2007.
     2.     C. O. Chui and K. C. Saraswat, "Nanoscale Germanium MOS Dielectrics and Junctions," Germanium-Based Technologies: From Materials to Devices (edited by C. Claeys and E. Simoen), Elsevier Science, Amsterdam, May 2007.
     1.     K. C. Saraswat, C. O. Chui, P. Kapur, T. Krishnamohan, A. Nayfeh, A. K. Okyay, and R. S. Shenoy, "Performance Limitations of Si CMOS and Alternatives for Nanoelectronics," Frontiers in Electronics: Proceedings of the WOFE-04 (edited by H. Iwai, Y. Nishi, M. S. Shur, and H. Wong), World Scientific, New Jersey, Aug 2006.

Invited Panels/Seminars/Talks

  1. C. O. Chui, "High Mobility Nanoelectronic Devices, Physics, and Technology," Special Seminar, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan, December 17, 2007.
  2. C. O. Chui, "High Mobility Germanium Nanoelectronic Devices and Technology," ECE294/296 Seminar, University of California, San Diego, CA, November 9, 2007.
  3. C. O. Chui, "Low Power Nanoelectronic Devices with High Carrier Mobility," Joint Seminar - Department of Electronic and Computer Engineering and SID HK Chapter, Hong Kong University of Science and Technology, Hong Kong, People's Republic of China, September 27, 2007.
  4. C. O. Chui, "Low Power Nanoelectronic Devices with High Carrier Mobility," Special Seminar, University of Hong Kong, Hong Kong, People's Republic of China, September 24, 2007.
  5. C. O. Chui, "Germanium CMOS Technologies with Nanoscale Dielectrics and Shallow Junctions," Special Seminar, Hong Kong University of Science and Technology, Hong Kong, People's Republic of China, December 16, 2005.
  6. C. O. Chui, "Opportunities and Challenges for New Technologies Beyond Planar Si-based CMOS," Workshop on New Channel Materials for Future MOSFET Technology, International SEMATECH, Washington, DC, December 4, 2005.
  7. C. O. Chui, "Germanium CMOS Technologies with Nanoscale Dielectrics and Shallow Junctions," Solid State Technology and Devices Seminar, University of California, Berkeley, CA, September 2, 2005.
  8. C. O. Chui, "Germanium CMOS Technologies with Nanoscale Dielectrics and Shallow Junctions," Special Seminar, Interuniversity MicroElectronics Center (IMEC), Leuven, Belgium, June 23, 2005.
  9. C. O. Chui, "Opportunities and Challenges for New Technologies Beyond Planar Si-based CMOS," Workshop on Future Prospects of Ge Device Technology, Interuniversity MicroElectronics Center (IMEC), Leuven, Belgium, June 21, 2005.
  10. C. O. Chui, "Advanced Germanium CMOS Technologies with Nanoscale Dielectrics and Shallow Junctions," Special Seminar, International SEMATECH, Austin, TX, May 12, 2005.
  11. C. O. Chui, "Advanced Germanium CMOS Technologies with Nanoscale Dielectrics and Shallow Junctions," American Vacuum Society (AVS) Thin Films 2004 Annual Symposium, San Jose, CA, October 14, 2004.
  12. C. O. Chui, "Advanced Germanium MOSFET Technologies with High-k Gate Dielectrics and Shallow Junctions," Special Seminar, Freescale Semiconductor, Austin, TX, May 19, 2004.
  13. C. O. Chui, "Germanium CMOS Technology Fundamentals," Special Seminar, Intel Corporation, Hillsboro, OR, May 18, 2004.
  14. C. O. Chui, "Novel Germanium Technology and Devices for High Performance MOSFETs," American Vacuum Society (AVS) Thin Film Users Group (TFUG) Technical Seminar, Sunnyvale, CA, February 18, 2004.
  15. C. O. Chui, "Novel Germanium Technology and Devices for High Performance MOSFETs," NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Teleseminar, February 5, 2004.
  16. C. O. Chui, "A Germanium NMOSFET Process Integrating Metal Gate and Improved High-k Dielectrics," Special Seminar, Intel Corporation, Hillsboro, OR, October 1, 2003.
  17. C. O. Chui, "Metal Gate High-k Ge Channel MOSFETs," International Workshop on Metal Gate/Workfunction Science and Engineering, Stanford University, Stanford, CA, August 28-29, 2003.
  18. C. O. Chui, "Metal Gate High-k Ge Channel MOSFETs," Special Seminar, Genus Inc., Sunnyvale, CA, August 27, 2003.
  19. C. O. Chui, "Advanced Germanium CMOS: Devices and the Enabling Technologies," High Mobility Channel Workshop, Stanford University, Stanford, CA, May 27, 2003.
  20. C. O. Chui, "Advanced Germanium CMOS: Devices and the Enabling Technologies," Special Seminar, Intel Corporation, Hillsboro, OR, May 20, 2003.
  21. C. O. Chui, "An Overview of the Sub-400°C Germanium MOS Technology and Devices," Solid State Technology and Devices Seminar, University of California, Berkeley, CA, February 14, 2003.
  22. C. O. Chui, "An Overview of the Sub-400°C Germanium MOS Technology," Special Seminar, Texas Instruments, Dallas, TX, November 21, 2002.
  23. C. O. Chui, "Si + ??: Strain, Ge, III-V, Etc. — What to Add When Scaling Ends?" IEEE 60th Annual Dev. Res. Conf. (DRC) Rump Session R-3 Panel, University of California, Santa Barbara, CA, June 25, 2002.

Issued Patents

  1. A. M. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, "Germanium Substrate-Type Materials and Approach Therefor," US Patent No. 7,495,313, issued on February 24, 2009.
  2. C. O. Chui, P. Majhi, W. Tsai, and J. T. Kavalieros, "Forming a Type I Heterostructure in a Group IV Semiconductor," US Patent No. 7,435,987, issued on October 14, 2008.
  3. C. O. Chui, K. C. Saraswat, B. B. Triplett, and P. C. McIntyre, "High-k Dielectric for Thermodynamically-Stable Substrate-Type Materials," US Patent No. 7,271,458, issued on September 18, 2007.